Validation of Damping Terminations for Signal Integrity Management in Digital Switching

Wei-Juet Wong; Antonio Cantoni

doi:10.1109/TENCON.2016.7848326

Validation of Damping Terminations for Signal Integrity Management in Digital Switching

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

Abstract

The Signal integrity (SI) of a digital signal transferred through a point-to-point printed circuit board interconnect is concerned with the design of the driver, receiver and interconnection so that requirements on rise/fall time, delay and overshoot meet the requirements relevant to each particular type of digital signal, be it a clock, address line or data line. One method for managing SI is through the control of resistors placed at the source and or destination. These are loosely referred to as damping termination techniques. In this paper, source series damping (SSD) and destination parallel damping (DPD) termination techniques are considered. Previous work has presented analytical models applicable to SSD and DPD that allow a designer to achieve certain quantifiable characteristics, such as settling time and overshoot. In this paper we present experimental results that have been used to validate results obtained with the analytical models. © 2016 IEEE.

Original language	English
Title of host publication	Proceedings of the 2016 IEEE Region 10 Conference
Editors	Dr. Arokiaswami Alphones, Dr. Rajnish Gupta, Dr. Michael Ong
Place of Publication	Singapore
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	1781-1785
Number of pages	5
ISBN (Electronic)	9781509025961
ISBN (Print)	21593450
DOIs	https://doi.org/10.1109/TENCON.2016.7848326
Publication status	Published - 8 Feb 2017
Event	2016 IEEE Region 10 Conference: TENCON 2016 - Marina Bay Sands, Singapore, Singapore Duration: 22 Nov 2016 → 25 Nov 2016

Conference

Conference	2016 IEEE Region 10 Conference
Country/Territory	Singapore
City	Marina Bay Sands, Singapore
Period	22/11/16 → 25/11/16

Access to Document

10.1109/TENCON.2016.7848326

Cite this

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title = "Validation of Damping Terminations for Signal Integrity Management in Digital Switching",

abstract = "The Signal integrity (SI) of a digital signal transferred through a point-to-point printed circuit board interconnect is concerned with the design of the driver, receiver and interconnection so that requirements on rise/fall time, delay and overshoot meet the requirements relevant to each particular type of digital signal, be it a clock, address line or data line. One method for managing SI is through the control of resistors placed at the source and or destination. These are loosely referred to as damping termination techniques. In this paper, source series damping (SSD) and destination parallel damping (DPD) termination techniques are considered. Previous work has presented analytical models applicable to SSD and DPD that allow a designer to achieve certain quantifiable characteristics, such as settling time and overshoot. In this paper we present experimental results that have been used to validate results obtained with the analytical models. {\textcopyright} 2016 IEEE.",

author = "Wei-Juet Wong and Antonio Cantoni",

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doi = "10.1109/TENCON.2016.7848326",

language = "English",

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pages = "1781--1785",

editor = "Alphones, {Dr. Arokiaswami} and Gupta, {Dr. Rajnish} and Ong, {Dr. Michael}",

booktitle = "Proceedings of the 2016 IEEE Region 10 Conference",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2016 IEEE Region 10 Conference : TENCON 2016 ; Conference date: 22-11-2016 Through 25-11-2016",

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Wong, W-J & Cantoni, A 2017, Validation of Damping Terminations for Signal Integrity Management in Digital Switching. in DA Alphones, DR Gupta & DM Ong (eds), Proceedings of the 2016 IEEE Region 10 Conference., 7848326, IEEE, Institute of Electrical and Electronics Engineers, Singapore, pp. 1781-1785, 2016 IEEE Region 10 Conference, Marina Bay Sands, Singapore, Singapore, 22/11/16. https://doi.org/10.1109/TENCON.2016.7848326

Validation of Damping Terminations for Signal Integrity Management in Digital Switching. / Wong, Wei-Juet; Cantoni, Antonio.
Proceedings of the 2016 IEEE Region 10 Conference. ed. / Dr. Arokiaswami Alphones; Dr. Rajnish Gupta; Dr. Michael Ong. Singapore: IEEE, Institute of Electrical and Electronics Engineers, 2017. p. 1781-1785 7848326.

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

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AB - The Signal integrity (SI) of a digital signal transferred through a point-to-point printed circuit board interconnect is concerned with the design of the driver, receiver and interconnection so that requirements on rise/fall time, delay and overshoot meet the requirements relevant to each particular type of digital signal, be it a clock, address line or data line. One method for managing SI is through the control of resistors placed at the source and or destination. These are loosely referred to as damping termination techniques. In this paper, source series damping (SSD) and destination parallel damping (DPD) termination techniques are considered. Previous work has presented analytical models applicable to SSD and DPD that allow a designer to achieve certain quantifiable characteristics, such as settling time and overshoot. In this paper we present experimental results that have been used to validate results obtained with the analytical models. © 2016 IEEE.

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BT - Proceedings of the 2016 IEEE Region 10 Conference

A2 - Alphones, Dr. Arokiaswami

A2 - Gupta, Dr. Rajnish

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Y2 - 22 November 2016 through 25 November 2016

ER -

Validation of Damping Terminations for Signal Integrity Management in Digital Switching

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