Validation of Damping Terminations for Signal Integrity Management in Digital Switching

Wei-Juet Wong, Antonio Cantoni

    Research output: Chapter in Book/Conference paperConference paper

    Abstract

    The Signal integrity (SI) of a digital signal transferred through a point-to-point printed circuit board interconnect is concerned with the design of the driver, receiver and interconnection so that requirements on rise/fall time, delay and overshoot meet the requirements relevant to each particular type of digital signal, be it a clock, address line or data line. One method for managing SI is through the control of resistors placed at the source and or destination. These are loosely referred to as damping termination techniques. In this paper, source series damping (SSD) and destination parallel damping (DPD) termination techniques are considered. Previous work has presented analytical models applicable to SSD and DPD that allow a designer to achieve certain quantifiable characteristics, such as settling time and overshoot. In this paper we present experimental results that have been used to validate results obtained with the analytical models. © 2016 IEEE.
    Original languageEnglish
    Title of host publicationProceedings of the 2016 IEEE Region 10 Conference
    EditorsDr. Arokiaswami Alphones, Dr. Rajnish Gupta, Dr. Michael Ong
    Place of PublicationSingapore
    PublisherIEEE, Institute of Electrical and Electronics Engineers
    Pages1781-1785
    Number of pages5
    ISBN (Print)21593450
    DOIs
    Publication statusPublished - 2016
    Event2016 IEEE Region 10 Conference: TENCON 2016 - Marina Bay Sands, Singapore, Singapore
    Duration: 22 Nov 201625 Nov 2016

    Conference

    Conference2016 IEEE Region 10 Conference
    CountrySingapore
    CityMarina Bay Sands, Singapore
    Period22/11/1625/11/16

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