Towards an FPGA based reconfigurable computing environment for neural network implementations

J. Zhu; G. J. Milne; B. K. Gunther

Towards an FPGA based reconfigurable computing environment for neural network implementations

J. Zhu, G. J. Milne, B. K. Gunther

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

Abstract

A different class of hardware environment, an FPGA-based reconfigurable computing environment for implementing neural networks, is developed. FPGAs offer speed comparable to dedicated and fixed hardware systems for parallel algorithm acceleration while, as with a software implementation, retaining a high degree of flexibility for device reconfiguration as the application demands. Such an FPGA based hardware environment is not only capable of implementing different size and forms of neural networks on the same hardware device, but it also capable of supporting the dynamic creation and modification of neural network topologies.

Original language	English
Title of host publication	IEE Conference Publication
Pages	661-666
Number of pages	6
Volume	2
Edition	470
Publication status	Published - 1 Dec 1999
Externally published	Yes
Event	9th International Conference on Artificial Neural Networks - Edinburgh, United Kingdom Duration: 7 Sept 1999 → 10 Sept 1999

Conference

Conference	9th International Conference on Artificial Neural Networks
Abbreviated title	ICANN '99
Country/Territory	United Kingdom
City	Edinburgh
Period	7/09/99 → 10/09/99

Cite this

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title = "Towards an FPGA based reconfigurable computing environment for neural network implementations",

abstract = "A different class of hardware environment, an FPGA-based reconfigurable computing environment for implementing neural networks, is developed. FPGAs offer speed comparable to dedicated and fixed hardware systems for parallel algorithm acceleration while, as with a software implementation, retaining a high degree of flexibility for device reconfiguration as the application demands. Such an FPGA based hardware environment is not only capable of implementing different size and forms of neural networks on the same hardware device, but it also capable of supporting the dynamic creation and modification of neural network topologies.",

author = "J. Zhu and Milne, {G. J.} and Gunther, {B. K.}",

year = "1999",

month = dec,

day = "1",

language = "English",

isbn = "0852967217",

volume = "2",

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booktitle = "IEE Conference Publication",

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note = "9th International Conference on Artificial Neural Networks, ICANN '99 ; Conference date: 07-09-1999 Through 10-09-1999",

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T1 - Towards an FPGA based reconfigurable computing environment for neural network implementations

AU - Zhu, J.

AU - Milne, G. J.

AU - Gunther, B. K.

PY - 1999/12/1

Y1 - 1999/12/1

N2 - A different class of hardware environment, an FPGA-based reconfigurable computing environment for implementing neural networks, is developed. FPGAs offer speed comparable to dedicated and fixed hardware systems for parallel algorithm acceleration while, as with a software implementation, retaining a high degree of flexibility for device reconfiguration as the application demands. Such an FPGA based hardware environment is not only capable of implementing different size and forms of neural networks on the same hardware device, but it also capable of supporting the dynamic creation and modification of neural network topologies.

AB - A different class of hardware environment, an FPGA-based reconfigurable computing environment for implementing neural networks, is developed. FPGAs offer speed comparable to dedicated and fixed hardware systems for parallel algorithm acceleration while, as with a software implementation, retaining a high degree of flexibility for device reconfiguration as the application demands. Such an FPGA based hardware environment is not only capable of implementing different size and forms of neural networks on the same hardware device, but it also capable of supporting the dynamic creation and modification of neural network topologies.

UR - http://www.scopus.com/inward/record.url?scp=0033322982&partnerID=8YFLogxK

M3 - Conference paper

AN - SCOPUS:0033322982

SN - 0852967217

SN - 9780852967218

VL - 2

SP - 661

EP - 666

BT - IEE Conference Publication

T2 - 9th International Conference on Artificial Neural Networks

Y2 - 7 September 1999 through 10 September 1999

ER -

Towards an FPGA based reconfigurable computing environment for neural network implementations

Abstract

Conference

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