Split-capacitance and conductance-frequency characteristics of SOI wafers in pseudo-MOSFET configuration

L. Pirro, A. Diab, I. Ionica, G. Ghibaudo, Lorenzo Faraone, S. Cristoloveanu

    Research output: Contribution to journalArticlepeer-review

    7 Citations (Scopus)


    © 1963-2012 IEEE. Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic.
    Original languageEnglish
    Pages (from-to)2717-2723
    JournalIEEE Transactions on Electron Devices
    Issue number9
    Publication statusPublished - 2015


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