Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers

L. Pirro, I. Ionica, X. Mescot, S. Cristoloveanu, G. Ghibaudo, Lorenzo Faraone

    Research output: Chapter in Book/Conference paperConference paper

    1 Citation (Scopus)

    Abstract

    © 2015 IEEE. We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.
    Original languageEnglish
    Title of host publicationEUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
    PublisherIEEE, Institute of Electrical and Electronics Engineers
    Pages249-252
    VolumeN/A
    ISBN (Print)9781479969111
    DOIs
    Publication statusPublished - 2015
    Event2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Bologna, Italy
    Duration: 26 Jan 201528 Jan 2015

    Conference

    Conference2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
    Abbreviated titleEUROSOI-ULIS 2015
    CountryItaly
    CityBologna
    Period26/01/1528/01/15

    Fingerprint Dive into the research topics of 'Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers'. Together they form a unique fingerprint.

  • Cite this

    Pirro, L., Ionica, I., Mescot, X., Cristoloveanu, S., Ghibaudo, G., & Faraone, L. (2015). Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers. In EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (Vol. N/A, pp. 249-252). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ULIS.2015.7063820