Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers

L. Pirro; I. Ionica; X. Mescot; S. Cristoloveanu; G. Ghibaudo; Lorenzo Faraone

doi:10.1109/ULIS.2015.7063820

Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers

L. Pirro, I. Ionica, X. Mescot, S. Cristoloveanu, G. Ghibaudo, Lorenzo Faraone

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

1 Citation (Scopus)

Abstract

© 2015 IEEE. We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.

Original language	English
Title of host publication	EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	249-252
Volume	N/A
ISBN (Print)	9781479969111
DOIs	https://doi.org/10.1109/ULIS.2015.7063820
Publication status	Published - 2015
Event	2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Bologna, Italy Duration: 26 Jan 2015 → 28 Jan 2015

Conference

Conference	2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
Abbreviated title	EUROSOI-ULIS 2015
Country/Territory	Italy
City	Bologna
Period	26/01/15 → 28/01/15

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Pirro, L., Ionica, I., Mescot, X., Cristoloveanu, S., Ghibaudo, G., & Faraone, L. (2015). Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers. In EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (Vol. N/A, pp. 249-252). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ULIS.2015.7063820

@inproceedings{072261e0ca1348d8b15f504f801f2fd5,

title = "Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers",

abstract = "{\textcopyright} 2015 IEEE. We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.",

author = "L. Pirro and I. Ionica and X. Mescot and S. Cristoloveanu and G. Ghibaudo and Lorenzo Faraone",

year = "2015",

doi = "10.1109/ULIS.2015.7063820",

language = "English",

isbn = "9781479969111",

volume = "N/A",

pages = "249--252",

booktitle = "EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), EUROSOI-ULIS 2015 ; Conference date: 26-01-2015 Through 28-01-2015",

}

Pirro, L, Ionica, I, Mescot, X, Cristoloveanu, S, Ghibaudo, G & Faraone, L 2015, Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers. in EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. vol. N/A, IEEE, Institute of Electrical and Electronics Engineers, pp. 249-252, 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Bologna, Italy, 26/01/15. https://doi.org/10.1109/ULIS.2015.7063820

Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers. / Pirro, L.; Ionica, I.; Mescot, X. et al.
EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Vol. N/A IEEE, Institute of Electrical and Electronics Engineers, 2015. p. 249-252.

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

TY - GEN

T1 - Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers

AU - Pirro, L.

AU - Ionica, I.

AU - Mescot, X.

AU - Cristoloveanu, S.

AU - Ghibaudo, G.

AU - Faraone, Lorenzo

PY - 2015

Y1 - 2015

N2 - © 2015 IEEE. We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.

AB - © 2015 IEEE. We investigate for the first time the quasi-static capacitance technique in pseudo-MOSFET configuration for the characterization of bare SOI wafers. We show the difference between the measurements performed with slow and fast ramp speed and compare them with split-CV characteristics. We discuss the impact of experimental parameters such as ramp speed, probe pressure and number of probes. Finally, we present an experimental procedure, based on an original physical model, to extract the interface trap density.

U2 - 10.1109/ULIS.2015.7063820

DO - 10.1109/ULIS.2015.7063820

M3 - Conference paper

SN - 9781479969111

VL - N/A

SP - 249

EP - 252

BT - EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

PB - IEEE, Institute of Electrical and Electronics Engineers

T2 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Y2 - 26 January 2015 through 28 January 2015

ER -

Pirro L, Ionica I, Mescot X, Cristoloveanu S, Ghibaudo G, Faraone L. Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers. In EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Vol. N/A. IEEE, Institute of Electrical and Electronics Engineers. 2015. p. 249-252 doi: 10.1109/ULIS.2015.7063820

Quasi-static capacitance measurements in pseudo-MOSFET configuration for Dit extraction in SOI wafers

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