3-D nonequilibrium Green's function simulations reveal the presence of oscillations of gate capacitance in multigate silicon nanowire FETs as the gate voltage is increased. These oscillations are due to the filling of successive energy subbands by electrons. The effect is due to both the 1-D distribution of the density of states and a change of position of the charge centroid location with gate voltage in the confined structure. This paper also proposes a model for the gate capacitance that allows one to better understand the nature of the oscillations and shows that the oscillations are mostly due to the particular shape of the 1-D density of states. The change of position of the charge centroid location contributes to a few percents in the total variation of the gate capacitance. The gate-capacitance to oxide-capacitance ratio remains low even at high gate voltages and worsens when the gate oxide thickness is decreased.