Operational efficiency of novel SISO shift register under thermal randomness in quantum-dot cellular automata design

Jadav Chandra Das, Debashis De

    Research output: Contribution to journalArticle

    27 Citations (Scopus)

    Abstract

    For nano scale logic circuit, device area and power consumption are the major concerns. In this paper, the design of an optimized SISO shift register is explored based on quantum-dot cellular automata (QCA) device. The design is achieved in a single layer. To design the shift register circuit, a new QCA D flip-flop has been proposed. These new D flip-flop has minimum cell count and lower device area over existing designs. The proposed shift register also outperforms the existing designs by reducing cell count and area. The power consumption by the proposed design is carried out that shows the low energy consumption nature of the circuit. Logic gate, QCA cell and device density have been considered to evaluate the circuit. Simulation timing diagram and truth table of the proposed circuits are compared which shows that all the designs are functioning efficiently. Stability under thermal randomness for all the designs are analyzed which shows the steadiness of the designs. The impacts of control input, i.e., clock on the designs are explored. Besides the defects in proposed QCA layouts are also identified and excelled for fault free implementation.

    Original languageEnglish
    Pages (from-to)4155-4168
    Number of pages14
    JournalMicrosystem Technologies
    Volume23
    Issue number9
    DOIs
    Publication statusPublished - 1 Sep 2017

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