Online testable conservative adder design in quantum dot cellular automata

A. Dey; K.K. Das; Debashis De; M. De

doi:10.1007/978-81-322-1817-3_38

Online testable conservative adder design in quantum dot cellular automata

A. Dey, K.K. Das, Debashis De, M. De

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

5 Citations (Scopus)

Abstract

Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions. © 2014 Springer.

Original language	English
Title of host publication	Lecture Notes in Electrical Engineering
Place of Publication	Netherlands
Publisher	Springer
Pages	385-393
Volume	298 LNEE
ISBN (Print)	9788132218166
DOIs	https://doi.org/10.1007/978-81-322-1817-3_38
Publication status	Published - 2014
Event	2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014 - Kolkata, India Duration: 22 Mar 2014 → 23 Mar 2014

Conference

Conference	2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014
Country/Territory	India
City	Kolkata
Period	22/03/14 → 23/03/14

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10.1007/978-81-322-1817-3_38

Cite this

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title = "Online testable conservative adder design in quantum dot cellular automata",

abstract = "Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions. {\textcopyright} 2014 Springer.",

author = "A. Dey and K.K. Das and Debashis De and M. De",

year = "2014",

doi = "10.1007/978-81-322-1817-3_38",

language = "English",

isbn = "9788132218166",

volume = "298 LNEE",

pages = "385--393",

booktitle = "Lecture Notes in Electrical Engineering",

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note = "2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014 ; Conference date: 22-03-2014 Through 23-03-2014",

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TY - GEN

T1 - Online testable conservative adder design in quantum dot cellular automata

AU - Dey, A.

AU - Das, K.K.

AU - De, Debashis

AU - De, M.

PY - 2014

Y1 - 2014

N2 - Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions. © 2014 Springer.

AB - Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions. © 2014 Springer.

U2 - 10.1007/978-81-322-1817-3_38

DO - 10.1007/978-81-322-1817-3_38

M3 - Conference paper

SN - 9788132218166

VL - 298 LNEE

SP - 385

EP - 393

BT - Lecture Notes in Electrical Engineering

PB - Springer

CY - Netherlands

T2 - 2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014

Y2 - 22 March 2014 through 23 March 2014

ER -

Online testable conservative adder design in quantum dot cellular automata

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