Garbage count minimization and low power, lossless conservative full adder design and its online testing in Quantum dot Cellular Automata is prime research interest of this work. Parity preserving reversible logic design as well as conservative logic design is a lossless paradigm in Nanotechnology. Errors can be detected by means of parity in conservative logic design. We introduce a conservative logic gate to design full adder with zero garbage count. The proposed two conservative logic gate (PCLG) is universal in nature. A tester reversible logic gate (TRLG) is designed to perform online test of proposed conservative logic gate (PCLG). We demonstrate the most promising two PCLG and a TRLG to design full adder and to online test of PCLG respectively. We compared our PCLG with well-known Fredkin gate in terms of implementation of thirteen standard functions. © 2014 Springer.
|Title of host publication||Lecture Notes in Electrical Engineering|
|Place of Publication||Netherlands|
|Publication status||Published - 2014|
|Event||2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014 - Kolkata, India|
Duration: 22 Mar 2014 → 23 Mar 2014
|Conference||2014 National Conference on Emerging Trends in Computing and Communication, ETCC 2014|
|Period||22/03/14 → 23/03/14|