Miniature cameras have become an integral feature of todays’ networked multimedia
consumer products. The ever increasing demand for low cost ultracompact
multimedia products is behind a growing effort towards integrating the
different circuit components of a camera system onto a single-chip. Such an integration
has become possible using microelectronics industry standard CMOS
fabrication process, which enables the fabrication of a CMOS pixel array together
with image processing circuitry. This thesis investigates the challenges of
integrating the image compression block into a CMOS camera. The direct implementation
of standard image compression algorithms like JPEG would result
in prohibitively large power and silicon area budgets because image compression
standards like JPEG are computationally and resource intensive.
To address this issue, this thesis introduces a number of hardware friendly image
compression schemes suitable for integration with CMOS imagers. Depending
on the target application, the different proposed schemes can offer different tradeoffs
between image quality, memory requirements, silicon and power budget.
A novel image compression processor based on predictive coding, adaptive
quantization and Quadrant Tree Decomposition (QTD) algorithms featuring low
complexity, low power, and high compactness was proposed and successfully implemented
in CMOS 0.35μm technology. The processor was integrated with a
64 × 64 Time-to-First Spike (TFS) Digital Pixel Sensor (DPS) array. The pro
cessor occupies 0.55mm2 silicon area and consumes 2 mW at 30 frames/s.
A second image compression scheme based on visual pattern image coding
(VPIC) and optimized for TFS DPS was subsequently proposed to further improve
image quality. Intensive multiplication and square root computations are
replaced with addition and shift operations. Image quality with Lena image reported
was 29 dB at 0.875 Bit-Per-Pixel (BPP).
The second part of the thesis explores potential applications of the newly introduced
compressive sampling paradigm. The latter addresses the inefficiency
of traditional signal processing pipeline which involves sampling followed by compression.
Exploiting compressive sampling theory, we propose novel spatial and
bit domain schemes that simultaneously sample and compress images with no
computation. Compressed images were reconstructed using l1-norm minimization
linear programming algorithms. Reported experimental results from the
implemented FPGA platform show reconstruction quality of 29 dB at 2 BPP for
256 × 256 image.
Finally, a novel image compression method based on vector quantization (VQ)
with shrunk codeword and reduced number of searches was proposed and implemented
in FPGA. The quality of Lena image reported was 29.26 dB at 0.5625
BPP, with 0.57 dB sacrifice but 96.54%, 96.72%, 96.8%, and 99.47% reduction
in the number of additions, subtractions, multiplications, and square roots operations,
respectively, required by conventional full search VQ.
|Qualification||Doctor of Philosophy|
|Publication status||Unpublished - 2012|