Novel technique for the analysis of jitter resulting in pulse stuffing schemes

In SDH and PDH networks, it is frequently necessary to recover a data clock from a gapped clock derived from stuff information present at the desynchronizer. In this paper, we present a comprehensive analysis of the timing jitter resulting from PLL type desynchronizers. This analysis is different from the conventional analysis where the jitter is represented simply using a phase error sequence. It is shown that such a simplified approach can not describe the jitter at the output of the desynchronizer. From a detailed analysis, it is also shown how the use of threshold modulation at the synchronizer reduces the low frequency jitter at the desynchronizer.