In SDH and PDH networks, it is frequently necessary to recover a data clock from a gapped clock derived from stuff information present at the desynchronizer. In this paper, we present a comprehensive analysis of the timing jitter resulting from PLL type desynchronizers. This analysis is different from the conventional analysis where the jitter is represented simply using a phase error sequence. It is shown that such a simplified approach can not describe the jitter at the output of the desynchronizer. From a detailed analysis, it is also shown how the use of threshold modulation at the synchronizer reduces the low frequency jitter at the desynchronizer.
|Number of pages||6|
|Publication status||Published - 1 Dec 1997|
|Event||Proceedings of the 1997 IEEE Global Telecommunications Conference. Part 2 (of 3) - Phoenix, AZ, USA|
Duration: 3 Nov 1997 → 8 Nov 1997
|Conference||Proceedings of the 1997 IEEE Global Telecommunications Conference. Part 2 (of 3)|
|City||Phoenix, AZ, USA|
|Period||3/11/97 → 8/11/97|