This paper proposes a new design for a frame sampling synchronizer and gives some typical applications for the device. It also discusses metastability which arises in the system due to the existence of asynchronous inputs. The motivation for the new design, details of the design and its modelling are also covered. Finally the jitter generated by the synchronizer is analyzed.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England|
Duration: 30 May 1994 → 2 Jun 1994