The authors consider fault-free digital circuits that can malfunction when asynchronous inputs have critical timing combinations resulting in metastable operation. This mode of failure is often overlooked in digital system design and reliability analysis. They survey developments in the study of metastable behavior and identify their relevance to digital system design and reliability. They describe and evaluate a number of techniques for reducing the probability of metastable failure, including the use of fast devices, extended decision time, a pausable clock, a Schmitt synchronizer, and redundancy and masking. They show that the use of extended decision time is the best technique for lowering the probability of synchronization failure.
|Number of pages||16|
|Journal||IEEE Design and Test of Computers|
|Publication status||Published - 1 Jan 1987|