In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
|Title of host publication||2009 IEEE INTERNATIONAL SOI CONFERENCE|
|Number of pages||2|
|Publication status||Published - 2009|
|Event||IEEE International SOI Conference 2009 - Foster City, Canada|
Duration: 5 Oct 2009 → 8 Oct 2009
|Conference||IEEE International SOI Conference 2009|
|Period||5/10/09 → 8/10/09|