Junctionless Nanowire Transistor (JNT): Properties and design guidelines

J. P. Colinge; A. Kranti; R. Yan; C. W. Lee; I. Ferain; R. Yu; N. Dehdashti Akhavan; P. Razavi

doi:10.1016/j.sse.2011.06.004

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

J. P. Colinge, A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi

School of Engineering

Research output: Contribution to journal › Article › peer-review

392 Citations (Scopus)

Abstract

Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.

Original language	English
Pages (from-to)	33-37
Number of pages	5
Journal	Solid-State Electronics
Volume	65-66
DOIs	https://doi.org/10.1016/j.sse.2011.06.004
Publication status	Published - 2011
Event	40th European Solid-State Device Research Conference (ESSDERC)/36th European Solid-State Circuits Conference (ESSCIRC) - Seville, Spain Duration: 14 Sept 2010 → 16 Sept 2010

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10.1016/j.sse.2011.06.004

Cite this

@article{f6f8a8d36edb4f4287609c29d20e13bb,

title = "Junctionless Nanowire Transistor (JNT): Properties and design guidelines",

abstract = "Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.",

keywords = "MOSFET, Multigate FET, Fin FET, Nanowire transistor, SENSITIVITY",

author = "Colinge, {J. P.} and A. Kranti and R. Yan and Lee, {C. W.} and I. Ferain and R. Yu and Akhavan, {N. Dehdashti} and P. Razavi",

year = "2011",

doi = "10.1016/j.sse.2011.06.004",

language = "English",

volume = "65-66",

pages = "33--37",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Pergamon",

note = "40th European Solid-State Device Research Conference (ESSDERC)/36th European Solid-State Circuits Conference (ESSCIRC) ; Conference date: 14-09-2010 Through 16-09-2010",

}

TY - JOUR

T1 - Junctionless Nanowire Transistor (JNT)

T2 - 40th European Solid-State Device Research Conference (ESSDERC)/36th European Solid-State Circuits Conference (ESSCIRC)

AU - Colinge, J. P.

AU - Kranti, A.

AU - Yan, R.

AU - Lee, C. W.

AU - Ferain, I.

AU - Yu, R.

AU - Akhavan, N. Dehdashti

AU - Razavi, P.

PY - 2011

Y1 - 2011

N2 - Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.

AB - Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.

KW - MOSFET

KW - Multigate FET

KW - Fin FET

KW - Nanowire transistor

KW - SENSITIVITY

U2 - 10.1016/j.sse.2011.06.004

DO - 10.1016/j.sse.2011.06.004

M3 - Article

SN - 0038-1101

VL - 65-66

SP - 33

EP - 37

JO - Solid-State Electronics

JF - Solid-State Electronics

Y2 - 14 September 2010 through 16 September 2010

ER -

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Abstract

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