Junctionless Nanowire Transistor (JNT): Properties and design guidelines

J. P. Colinge, A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi

Research output: Contribution to journalArticlepeer-review

321 Citations (Scopus)

Abstract

Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.

Original languageEnglish
Pages (from-to)33-37
Number of pages5
JournalSolid-State Electronics
Volume65-66
DOIs
Publication statusPublished - 2011
Event40th European Solid-State Device Research Conference (ESSDERC)/36th European Solid-State Circuits Conference (ESSCIRC) - Seville, Spain
Duration: 14 Sep 201016 Sep 2010

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