Junctionless Multiple-Gate Transistors for Analog Applications

Rodrigo Trevisoli Doria, Marcelo Antonio Pavanello, Renan Doria Trevisoli, Michelly de Souza, Chi-Woo Lee, Isabelle Ferain, Nima Dehdashti Akhavan, Ran Yan, Pedram Razavi, Ran Yu, Abhinav Kranti, Jean-Pierre Colinge

Research output: Contribution to journalArticlepeer-review

244 Citations (Scopus)


This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W-fin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V-EA and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V-EA and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Original languageEnglish
Pages (from-to)2511-2519
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number8
Publication statusPublished - Aug 2011
Externally publishedYes


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