Investigation of high-performance sub-50 nm junctionless nanowire transistors

Ran Yan, Abhinav Kranti, Isabelle Ferain, Chi-Woo Lee, Ran Yu, Nima Dehdashti, Pedram Razavi, Jean-Pierre Colinge

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25 nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25 nm, a 30-40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive. (C) 2011 Elsevier Ltd. All rights reserved.

Original languageEnglish
Pages (from-to)1166-1171
Number of pages6
JournalMicroelectronics Reliability
Volume51
Issue number7
DOIs
Publication statusPublished - Jul 2011
Externally publishedYes

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