Integrating the verification of timing, performance and correctness properties of concurrent systems

A. Cerone; D. A. Kearney; G. J. Milne

doi:10.1109/CSD.1998.657544

Integrating the verification of timing, performance and correctness properties of concurrent systems

A. Cerone, D. A. Kearney, G. J. Milne

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

6 Citations (Scopus)

Abstract

Previous methods of verification tend to keep cor- rectness, timing and performance separate. In this paper we present a process algebra based methodology for the integrated modelling and verification of correct- ness, performance and timing properties of concurrent systems. We have applied the method to the domain of asynchronous hardware and used an asynchronous micropipeline as an illustrative example.

Original language	English
Title of host publication	Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	109-119
Number of pages	11
Volume	1998-March
ISBN (Electronic)	0818683503, 9780818683503
DOIs	https://doi.org/10.1109/CSD.1998.657544
Publication status	Published - 1 Jan 1998
Externally published	Yes
Event	1998 International Conference on Application of Concurrency to System Design - Fukushima, Japan Duration: 23 Mar 1998 → 26 Mar 1998

Conference

Conference	1998 International Conference on Application of Concurrency to System Design
Abbreviated title	ACSD 1998
Country/Territory	Japan
City	Fukushima
Period	23/03/98 → 26/03/98

Access to Document

10.1109/CSD.1998.657544

Cite this

Cerone, A., Kearney, D. A., & Milne, G. J. (1998). Integrating the verification of timing, performance and correctness properties of concurrent systems. In Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998 (Vol. 1998-March, pp. 109-119). Article 657544 IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/CSD.1998.657544

@inproceedings{4eedccb2c7e046d8b9194601ebc9ff54,

title = "Integrating the verification of timing, performance and correctness properties of concurrent systems",

abstract = "Previous methods of verification tend to keep cor- rectness, timing and performance separate. In this paper we present a process algebra based methodology for the integrated modelling and verification of correct- ness, performance and timing properties of concurrent systems. We have applied the method to the domain of asynchronous hardware and used an asynchronous micropipeline as an illustrative example.",

author = "A. Cerone and Kearney, {D. A.} and Milne, {G. J.}",

year = "1998",

month = jan,

day = "1",

doi = "10.1109/CSD.1998.657544",

language = "English",

volume = "1998-March",

pages = "109--119",

booktitle = "Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1998 International Conference on Application of Concurrency to System Design , ACSD 1998 ; Conference date: 23-03-1998 Through 26-03-1998",

}

Cerone, A, Kearney, DA & Milne, GJ 1998, Integrating the verification of timing, performance and correctness properties of concurrent systems. in Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998. vol. 1998-March, 657544, IEEE, Institute of Electrical and Electronics Engineers, pp. 109-119, 1998 International Conference on Application of Concurrency to System Design , Fukushima, Japan, 23/03/98. https://doi.org/10.1109/CSD.1998.657544

Integrating the verification of timing, performance and correctness properties of concurrent systems. / Cerone, A.; Kearney, D. A.; Milne, G. J.
Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998. Vol. 1998-March IEEE, Institute of Electrical and Electronics Engineers, 1998. p. 109-119 657544.

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

TY - GEN

T1 - Integrating the verification of timing, performance and correctness properties of concurrent systems

AU - Cerone, A.

AU - Kearney, D. A.

AU - Milne, G. J.

PY - 1998/1/1

Y1 - 1998/1/1

N2 - Previous methods of verification tend to keep cor- rectness, timing and performance separate. In this paper we present a process algebra based methodology for the integrated modelling and verification of correct- ness, performance and timing properties of concurrent systems. We have applied the method to the domain of asynchronous hardware and used an asynchronous micropipeline as an illustrative example.

AB - Previous methods of verification tend to keep cor- rectness, timing and performance separate. In this paper we present a process algebra based methodology for the integrated modelling and verification of correct- ness, performance and timing properties of concurrent systems. We have applied the method to the domain of asynchronous hardware and used an asynchronous micropipeline as an illustrative example.

UR - http://www.scopus.com/inward/record.url?scp=28044453888&partnerID=8YFLogxK

U2 - 10.1109/CSD.1998.657544

DO - 10.1109/CSD.1998.657544

M3 - Conference paper

AN - SCOPUS:28044453888

VL - 1998-March

SP - 109

EP - 119

BT - Proceedings - 1998 International Conference on Application of Concurrency to System Design, ACSD 1998

PB - IEEE, Institute of Electrical and Electronics Engineers

T2 - 1998 International Conference on Application of Concurrency to System Design

Y2 - 23 March 1998 through 26 March 1998

ER -

Integrating the verification of timing, performance and correctness properties of concurrent systems

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this