High-Density Memristor-CMOS Ternary Logic Family

Xiao Yuan Wang, Peng Fei Zhou, Jason K. Eshraghian, Chih Yang Lin, Herbert Ho Ching Iu, Ting Chang Chang, Sung Mo Kang

Research output: Contribution to journalArticlepeer-review

15 Citations (Web of Science)


This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Original languageEnglish
Article number9214881
Pages (from-to)264-274
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number1
Publication statusPublished - Jan 2021


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