FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays

Xiao Yuan Wang, Zhi Ru Wu, Peng Fei Zhou, Herbert Ho Ching Iu, Sung Mo Kang, Jason K. Eshraghian

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25-240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1-3 line decoder and a ternary 2-9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.

Original languageEnglish
Pages (from-to)3501-3511
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume69
Issue number9
Early online date19 Jan 2022
DOIs
Publication statusPublished - 1 Sep 2022

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