Abstract
A framework is presented in which circuit timing issues may be isolated, specified and formally verified. This approach to reasoning about time differs from current timing analysis work in that a complete formal analysis infrastructure has been created rather than a single timing analysis tool. The infrastructure has been used to discover methodologies for rigorously reasoning about the temporal properties of digital hardware. The modelling framework is based on CIRCAL, a formal concurrent process model developed for the purpose of rigorously describing and analysing properties of highly complex concurrent systems such as those found in integrated circuit hardware.
| Original language | English |
|---|---|
| Journal | Institution of Electrical Engineers. Colloquium. |
| Issue number | 24 |
| Publication status | Published - 1 Dec 1990 |
| Externally published | Yes |
| Event | Colloquium on Temporal Reasoning - London, Engl Duration: 31 Jan 1990 → 31 Jan 1990 |