Design of QCA based Programmable Logic Array using decoder

Debashis De; T. Purkayastha; T. Chattopadhyay

doi:10.1016/j.mejo.2016.06.005

Design of QCA based Programmable Logic Array using decoder

Debashis De, T. Purkayastha, T. Chattopadhyay

Research output: Contribution to journal › Article

10 Citations (Scopus)

Abstract

© 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.

Original language	English
Pages (from-to)	92-107
Journal	Microelectronics Journal
Volume	55
DOIs	https://doi.org/10.1016/j.mejo.2016.06.005
Publication status	Published - 2016

Access to Document

10.1016/j.mejo.2016.06.005

Fingerprint Dive into the research topics of 'Design of QCA based Programmable Logic Array using decoder'. Together they form a unique fingerprint.

Cite this

@article{95b572b658f446c0a85616978947ab3a,

title = "Design of QCA based Programmable Logic Array using decoder",

abstract = "{\textcopyright} 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.",

author = "Debashis De and T. Purkayastha and T. Chattopadhyay",

year = "2016",

doi = "10.1016/j.mejo.2016.06.005",

language = "English",

volume = "55",

pages = "92--107",

journal = "Microelectronics Journal",

issn = "0026-2692",

publisher = "Elsevier",

}

TY - JOUR

T1 - Design of QCA based Programmable Logic Array using decoder

AU - De, Debashis

AU - Purkayastha, T.

AU - Chattopadhyay, T.

PY - 2016

Y1 - 2016

N2 - © 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.

AB - © 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.

U2 - 10.1016/j.mejo.2016.06.005

DO - 10.1016/j.mejo.2016.06.005

M3 - Article

VL - 55

SP - 92

EP - 107

JO - Microelectronics Journal

JF - Microelectronics Journal

SN - 0026-2692

ER -