TY - JOUR
T1 - Design of QCA based Programmable Logic Array using decoder
AU - De, Debashis
AU - Purkayastha, T.
AU - Chattopadhyay, T.
PY - 2016/9/1
Y1 - 2016/9/1
N2 - © 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.
AB - © 2016 Elsevier LtdA novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.
U2 - 10.1016/j.mejo.2016.06.005
DO - 10.1016/j.mejo.2016.06.005
M3 - Article
SN - 0026-2692
VL - 55
SP - 92
EP - 107
JO - Microelectronics Journal
JF - Microelectronics Journal
ER -