Complex adder designs in Quantum Dot-Cellular Automata (QCA) are primary focus of researchers on lowering cell-count, delay and QCA gates. The cell count, area and delay of two input adders such as Brent-Kung, Ladner-Ficher, Han-Carlson and Kogg-Stone are at least doubles when three numbers are added, compared to adding two numbers. Besides, the interconnected QCA wires for these adders decrease the addition time. To eliminate this problem, a new 4-bit Carry Save Adder (CSA) is proposed in this paper. To design the CSA circuit, a novel design of full adder circuit using 5-input majority gate (MV) has been proposed. The proposed design has around 11.76% improvement in cell count and 33.33% improvement in latency compared to the existing QCA full-adders. Besides, when three binary numbers are added, CSA is far more advantageous compared to similar addition using two input prefix adders, in terms of QCA cell count, area and clock delay. Compared to 4-bit traditional adders, proposed CSA has around 80% decreases in overall circuit cost. The QCA layout of CSA is the first one of its kind. An improved QCA layout of a 4-bit ripple carry adder (RCA) is also proposed in this paper. The RCA has around 7.6% improvement in cell count, 33.33% improvement in latency and around 5.56% improvement in overall cost over compared to the existing layouts.