Design for verifiability

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3 Citations (Scopus)


The concept of Design for Verifiability is introduced as a means of attacking the complexity problem encountered when verifying the correctness of hardware designs using mathematical proof techniques. The inherent complexity of systems implemented as integrated circuits results in a comparable descriptive complexity when modelling them in any framework which supports formal verification. Performing formal verification then rapidly becomes intractable as a consequence of this descriptive complexity. In this paper we propose a strategy for dealing, at least in part, with this problem. We advocate the use of a particular design strategy involving the use of structural design rules which constrain the behaviour of a design resulting in a less complex design verification. The term Design for Verifiability is used to capture this concept in an analogous way to the term Design for Testability.

Original languageEnglish
Title of host publicationHardware Specification, Verification and Synthesis
Subtitle of host publicationMathematical Aspects - Mathematical Sciences Institute Workshop, Proceedings
EditorsMiriam Leeser, Geoffrey Brown
PublisherSpringer-Verlag Berlin
Number of pages13
ISBN (Print)9780387972268
Publication statusPublished - 1 Jan 1990
Externally publishedYes
EventMathematical Sciences Institute Workshop on Hardware Specification, Verification and Synthesis, 1989 - Ithaca, United States
Duration: 5 Jul 19897 Jul 1989

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume408 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


ConferenceMathematical Sciences Institute Workshop on Hardware Specification, Verification and Synthesis, 1989
Country/TerritoryUnited States


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