@article{69a17d1006c541a0a0167090018963bc,
title = "Design and Application of Memristive Balanced Ternary Univariate Logic Circuit",
abstract = "This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.",
keywords = "balanced ternary, combinational logic circuit, memristor, univariate logic",
author = "Xiaoyuan Wang and Xinrui Zhang and Chuantao Dong and Nath, \{Shimul Kanti\} and Iu, \{Herbert Ho Ching\}",
note = "Funding Information: This work was supported in part by the National Natural Science Foundation of China under Grant 61871429, in part by the Natural Science Foundation of Zhejiang Provuince under Grant LY18F010012. Publisher Copyright: {\textcopyright} 2023 by the authors.",
year = "2023",
month = sep,
day = "30",
doi = "10.3390/mi14101895",
language = "English",
volume = "14",
journal = "Micromachines",
issn = "2072-666X",
publisher = "M D P I AG",
number = "10",
}