Abstract
This paper addresses the selection of a suitable dither sequence for given Sigma-Delta modulator-demodulator characteristics. We have shown using mathematical analysis and simulations, that it is possible to select an appropriate dither sequence which produces minimum worst case quantization noise power for a specified input d.c. value dynamic range and low-pass filter bandwidth. In this approach, pseudo random sequences are used for dithering. The optimum dither sequence periodicity is selected on the basis of the range of input d.c. values and the filter bandwidth. The conditions under which optimum dithering schemes are superior to adaptive schemes are also identified in the paper. It is possible to extend the analysis presented in the paper to higher order modulators.
| Original language | English |
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| Pages (from-to) | 57-60 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 1 Jan 1996 |
| Event | Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: 12 May 1996 → 15 May 1996 |