BEHAVIOURAL DESCRIPTION AND VLSI VERIFICATION.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, but also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.

Original languageEnglish
Pages (from-to)87-97
Number of pages11
JournalIEE Proceedings I: Solid State and Electron Devices
Volume133
Issue number3
DOIs
Publication statusPublished - 1 Jan 1986
Externally publishedYes

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