BEHAVIOURAL DESCRIPTION AND VLSI VERIFICATION.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, but also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.

Original languageEnglish
Pages (from-to)87-97
Number of pages11
JournalIEE Proceedings I: Solid State and Electron Devices
Volume133
Issue number3
DOIs
Publication statusPublished - 1 Jan 1986
Externally publishedYes

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Computer hardware description languages
Specifications
Formal verification

Cite this

@article{7081f9ef870740eabf4534b492ff10c4,
title = "BEHAVIOURAL DESCRIPTION AND VLSI VERIFICATION.",
abstract = "Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, but also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.",
author = "Milne, {G. J.}",
year = "1986",
month = "1",
day = "1",
doi = "10.1049/ip-i-1.1986.0020",
language = "English",
volume = "133",
pages = "87--97",
journal = "IEE Proceedings I: Solid State and Electron Devices",
issn = "0143-7100",
publisher = "The Institution of Engineering and Technology",
number = "3",

}

BEHAVIOURAL DESCRIPTION AND VLSI VERIFICATION. / Milne, G. J.

In: IEE Proceedings I: Solid State and Electron Devices, Vol. 133, No. 3, 01.01.1986, p. 87-97.

Research output: Contribution to journalArticle

TY - JOUR

T1 - BEHAVIOURAL DESCRIPTION AND VLSI VERIFICATION.

AU - Milne, G. J.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, but also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.

AB - Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilises simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description languages. These differ from inherently structural hardware description languages (HDLs) in that they not only allow behaviour and structure to be described, but also support formal behavioural analysis using mathematical techniques. Necessary features of a behavioural description language are presented and the application of this language to VLSI description, design and verification is illustrated.

UR - http://www.scopus.com/inward/record.url?scp=0022739914&partnerID=8YFLogxK

U2 - 10.1049/ip-i-1.1986.0020

DO - 10.1049/ip-i-1.1986.0020

M3 - Article

VL - 133

SP - 87

EP - 97

JO - IEE Proceedings I: Solid State and Electron Devices

JF - IEE Proceedings I: Solid State and Electron Devices

SN - 0143-7100

IS - 3

ER -