Abstract
Validation of VLSI design correctness by formal proof is an alternative to the traditional approach which utilizes simulation. Formal verification requires the description of the behavior of designs and design specifications, resulting in the development of behavioral description. These differ from inherently structural hardware description languages HDLs in that they not only allow behavior and structure to be described, they also support formal behavioral analysis using mathematical techniques. Necessary features of a behavioral description language are presented and the application of this language to VLSI description, design and verification is illustrated.
| Original language | English |
|---|---|
| Pages (from-to) | 127-137 |
| Number of pages | 11 |
| Journal | IEE Proceedings E: Computers and Digital Techniques |
| Volume | 133 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1 Jan 1986 |
| Externally published | Yes |