Timing jitter and phase noise are important design considerations in most electronic systems, particularly communication systems. The desire for faster transmission speeds and higher levels of integration, combined with lower signal levels and denser circuit boards has placed greater emphasis on managing problems related to phase noise, timing jitter, and timing distribution. This thesis reports original work on phase noise modelling in electronic systems. A new model is proposed which predicts the up-conversion of baseband noise to the carrier frequency in RF amplifiers. The new model is validated by comparing the predicted phase noise performance to experimental measurements as it applies to a common emitter (CE), bipolar junction transistor (BJT) amplifier. The results show that the proposed model correctly predicts the measured phase noise, including the shaping of the noise about the carrier frequency, and the dependence of phase noise on the amplifier parameters. In addition, new work relating to timing transfer in digital communication systems is presented. A new clock recovery algorithm is proposed for decoding timing information encoded using the synchronous residual time-stamp (SRTS) method. Again, theoretical analysis is verified by comparison with an experimental implementation. The results show that the new algorithm correctly recovers the source clock at the destination, and satisfies the jitter specification set out by the ITU-T for G.702 signals.
|Qualification||Doctor of Philosophy|
|Publication status||Unpublished - 2004|