An investigation into fabrication technologies for vertical GaN devices

Azlan Baharin

    Research output: ThesisDoctoral Thesis

    643 Downloads (Pure)


    [Truncated abstract] Vertical transistors using GaN have significant advantages over planar devices in high power, high current applications. The principal focus of this thesis is to use the GaN n-p vertical diode as a model to understand the fabrication issues involved in vertical transistors. GaN n-p vertical diodes have been fabricated using Si ion implantation into p-doped material on a p+-buried layer. Ion implantation is widely used in semiconductor device technology because it offers precise control of the concentration and depth of dopants that are inserted in a specific area of the wafer and the technique can be easily applied to batch processing; GaN implantation technology is still in the developing phase and it is hoped that not too far in the future, ion implantation can also become a practical process for GaN-based devices. Amongst the major challenges faced for ion implantation in GaN is the extremely high and impractical annealing temperature (above 1500 °C) required for a complete recovery of implantation damage. This work has shown that a much lower annealing temperature of 1260 °C can be sufficient to minimise the damage and electrically activate the implanted dopants. In the first round of device fabrication, vertical diodes were successfully obtained using Si implantation with a variety of energies and doses.
    Original languageEnglish
    QualificationDoctor of Philosophy
    Publication statusUnpublished - 2011

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