An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic

R. Lin, K. Nakano, S. Olariu, A.Y. Zomaya

Research output: Chapter in Book/Conference paperConference paper

Original languageEnglish
Title of host publicationProceedings of the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Proce
EditorsM. Atallah
Place of PublicationU.S.A.
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages273-277
Volume1
EditionSan Juan, Puerto Rico, U.S.A.
ISBN (Print)0769501435
Publication statusPublished - 1999
EventAn Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic - San Juan, Puerto Rico, U.S.A.
Duration: 1 Jan 1999 → …

Conference

ConferenceAn Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic
Period1/01/99 → …

Cite this

Lin, R., Nakano, K., Olariu, S., & Zomaya, A. Y. (1999). An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. In M. Atallah (Ed.), Proceedings of the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Proce (San Juan, Puerto Rico, U.S.A. ed., Vol. 1, pp. 273-277). IEEE, Institute of Electrical and Electronics Engineers.