Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC

Y. Chen, Q. Zhang, Y. Ge, Y. Hu, J. Chen, N. Ding, X. Zeng, David Huang

    Research output: Chapter in Book/Conference paperConference paper

    2 Citations (Scopus)
    Original languageEnglish
    Title of host publication2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
    Place of PublicationUSA
    PublisherIEEE, Institute of Electrical and Electronics Engineers
    Pages932-935
    ISBN (Print)9781479900664
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE 56th International Midwest Symposium on Circuits and Systems - Columbus, United States
    Duration: 4 Aug 20137 Aug 2013

    Conference

    Conference2013 IEEE 56th International Midwest Symposium on Circuits and Systems
    CountryUnited States
    CityColumbus
    Period4/08/137/08/13

    Cite this

    Chen, Y., Zhang, Q., Ge, Y., Hu, Y., Chen, J., Ding, N., Zeng, X., & Huang, D. (2013). Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 932-935). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/MWSCAS.2013.6674803