Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC

Y. Chen; Q. Zhang; Y. Ge; Y. Hu; J. Chen; N. Ding; X. Zeng; David Huang

doi:10.1109/MWSCAS.2013.6674803

Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC

Y. Chen, Q. Zhang, Y. Ge, Y. Hu, J. Chen, N. Ding, X. Zeng, David Huang

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

Original language	English
Title of host publication	2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
Place of Publication	USA
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	932-935
ISBN (Print)	9781479900664
DOIs	https://doi.org/10.1109/MWSCAS.2013.6674803
Publication status	Published - 2013
Event	2013 IEEE 56th International Midwest Symposium on Circuits and Systems - Columbus, United States Duration: 4 Aug 2013 → 7 Aug 2013

Conference

Conference	2013 IEEE 56th International Midwest Symposium on Circuits and Systems
Country/Territory	United States
City	Columbus
Period	4/08/13 → 7/08/13

Access to Document

10.1109/MWSCAS.2013.6674803

Cite this

Chen, Y., Zhang, Q., Ge, Y., Hu, Y., Chen, J., Ding, N., Zeng, X., & Huang, D. (2013). Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 932-935). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/MWSCAS.2013.6674803

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title = "Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC",

author = "Y. Chen and Q. Zhang and Y. Ge and Y. Hu and J. Chen and N. Ding and X. Zeng and David Huang",

year = "2013",

doi = "10.1109/MWSCAS.2013.6674803",

language = "English",

isbn = "9781479900664",

pages = "932--935",

booktitle = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems ; Conference date: 04-08-2013 Through 07-08-2013",

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Chen, Y, Zhang, Q, Ge, Y, Hu, Y, Chen, J, Ding, N, Zeng, X & Huang, D 2013, Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. in 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, Institute of Electrical and Electronics Engineers, USA, pp. 932-935, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, Columbus, Ohio, United States, 4/08/13. https://doi.org/10.1109/MWSCAS.2013.6674803

Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. / Chen, Y.; Zhang, Q.; Ge, Y. et al.
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). USA: IEEE, Institute of Electrical and Electronics Engineers, 2013. p. 932-935.

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

TY - GEN

T1 - Alogrithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC

AU - Chen, Y.

AU - Zhang, Q.

AU - Ge, Y.

AU - Hu, Y.

AU - Chen, J.

AU - Ding, N.

AU - Zeng, X.

AU - Huang, David

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M3 - Conference paper

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BT - 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - USA

T2 - 2013 IEEE 56th International Midwest Symposium on Circuits and Systems

Y2 - 4 August 2013 through 7 August 2013

ER -