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A Scalable VLSI Architecture for Binary Prefix Sums

  • R. Lin
  • , S. Olariu
  • , J. Pinotti
  • , J.L. Schwing
  • , A.Y. Zomaya

Research output: Chapter in Book/Conference paperConference paperpeer-review

Original languageEnglish
Title of host publicationJoint 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing
Place of PublicationUSA
PublisherIEE Computer Press
Pages333-337
Volume1
EditionOrland, Florida
ISBN (Print)0 8186 8403 8
Publication statusPublished - 1998
EventA Scalable VLSI Architecture for Binary Prefix Sums - Orland, Florida
Duration: 1 Jan 1998 → …

Conference

ConferenceA Scalable VLSI Architecture for Binary Prefix Sums
Period1/01/98 → …

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