A Scalable VLSI Architecture for Binary Prefix Sums

R. Lin, S. Olariu, J. Pinotti, J.L. Schwing, A.Y. Zomaya

Research output: Chapter in Book/Conference paper › Conference paper › peer-review

Original language	English
Title of host publication	Joint 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing
Place of Publication	USA
Publisher	IEE Computer Press
Pages	333-337
Volume	1
Edition	Orland, Florida
ISBN (Print)	0 8186 8403 8
Publication status	Published - 1998
Event	A Scalable VLSI Architecture for Binary Prefix Sums - Orland, Florida Duration: 1 Jan 1998 → …

Conference	A Scalable VLSI Architecture for Binary Prefix Sums
Period	1/01/98 → …

Cite this

@inproceedings{d737d21114b94f73a6e65f80a9b3096a,

title = "A Scalable VLSI Architecture for Binary Prefix Sums",

author = "R. Lin and S. Olariu and J. Pinotti and J.L. Schwing and A.Y. Zomaya",

year = "1998",

language = "English",

isbn = "0 8186 8403 8",

volume = "1",

pages = "333--337",

booktitle = "Joint 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing",

publisher = "IEE Computer Press",

edition = "Orland, Florida",

note = "A Scalable VLSI Architecture for Binary Prefix Sums ; Conference date: 01-01-1998",

}

TY - GEN

T1 - A Scalable VLSI Architecture for Binary Prefix Sums

AU - Lin, R.

AU - Olariu, S.

AU - Pinotti, J.

AU - Schwing, J.L.

AU - Zomaya, A.Y.

PY - 1998

Y1 - 1998

M3 - Conference paper

SN - 0 8186 8403 8

VL - 1

SP - 333

EP - 337

BT - Joint 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing

PB - IEE Computer Press

CY - USA

T2 - A Scalable VLSI Architecture for Binary Prefix Sums

Y2 - 1 January 1998

ER -