TY - JOUR
T1 - A novel dual-directional DTSCR in twin-well process for ultra-low-voltage ESD protection
AU - Gu, Xiaofeng
AU - Xu, Jian
AU - Liang, Hailian
AU - Liu, Junliang
AU - Wang, Dong
AU - Dong, Shurong
AU - Lei, Wen
AU - Liou, Juin J.
N1 - Publisher Copyright:
© 2023 Elsevier Ltd
PY - 2024/2
Y1 - 2024/2
N2 - By embedding additional NPN- and PNP- type bipolar junction transistors into a diode-triggered silicon-controlled rectifier (DTSCR) with single-directional ESD protection, we propose and implement a novel dual-directional DTSCR (DDTSCR) by using the twin-well process in a 0.18-µm CMOS process that provides highly efficient ultra-low-voltage ESD protection. Compared to conventional DTSCRs, the failure current of the proposed DDTSCR increases from 4.5 A to 5.6 A, successfully passing the ESD level tests of human body model at 8 kV and machine model at 650 V. Owing to its unique structural design and metal routing, the ESD protection efficiency of the DDTSCR is twice that of the DTSCR. By adopting a new E-shaped layout (DDTSCR-E), the failure current under positive stress can increase further to 6.6 A. In order to verify the ESD protection performance stabilization with different processes, the DDTSCR-E is fabricated in the 0.18-µm BCD, 0.18-µm and 21-nm CMOS processes, respectively. The trigger voltage of DDTSCR-E is found more stable than other ESD characteristics during the process migration. The high efficiency, the strong ESD robustness and the stable process migration make the proposed DDTSCR a promising ESD protection device for ultra-low-voltage integrated circuits.
AB - By embedding additional NPN- and PNP- type bipolar junction transistors into a diode-triggered silicon-controlled rectifier (DTSCR) with single-directional ESD protection, we propose and implement a novel dual-directional DTSCR (DDTSCR) by using the twin-well process in a 0.18-µm CMOS process that provides highly efficient ultra-low-voltage ESD protection. Compared to conventional DTSCRs, the failure current of the proposed DDTSCR increases from 4.5 A to 5.6 A, successfully passing the ESD level tests of human body model at 8 kV and machine model at 650 V. Owing to its unique structural design and metal routing, the ESD protection efficiency of the DDTSCR is twice that of the DTSCR. By adopting a new E-shaped layout (DDTSCR-E), the failure current under positive stress can increase further to 6.6 A. In order to verify the ESD protection performance stabilization with different processes, the DDTSCR-E is fabricated in the 0.18-µm BCD, 0.18-µm and 21-nm CMOS processes, respectively. The trigger voltage of DDTSCR-E is found more stable than other ESD characteristics during the process migration. The high efficiency, the strong ESD robustness and the stable process migration make the proposed DDTSCR a promising ESD protection device for ultra-low-voltage integrated circuits.
KW - Diode-triggered silicon-controlled rectifier
KW - Dual-directional ESD protection
KW - Electrostatic discharge
KW - Robustness
UR - http://www.scopus.com/inward/record.url?scp=85180548901&partnerID=8YFLogxK
U2 - 10.1016/j.sse.2023.108847
DO - 10.1016/j.sse.2023.108847
M3 - Article
AN - SCOPUS:85180548901
SN - 0038-1101
VL - 212
JO - Solid-State Electronics
JF - Solid-State Electronics
M1 - 108847
ER -