A detailed analysis of phase locked loops used in clock jitter reduction

S Abeysekera, A Cantoni

Research output: Chapter in Book/Conference paperChapterpeer-review

Original languageEnglish
Title of host publicationDigital Signal Processing for Communication Systems
EditorsT Wysocki, H Razavi, B Honary
PublisherSpringer
Pages243-253
Number of pages11
Volume1
ISBN (Print)978-1-4615-6119-4
Publication statusPublished - 1996

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